Hardware implementation of genetic algorithms is critical for those applications, which require real-time operation. When studying genetic algorithms' hardware implementation, this paper presents an FPGA (Field Programmable Gate Array)-based hardware architecture, which is capable of population storage, selection, crossover, mutation, fitness evaluation, and survival determination. Moreover, utilizing the built-in multipliers and Block Dual-RAM as well as pipeline pattern, the method introduced in this paper accelerates the system's operation and resolves the conflict between the resources and the processing speed. The whole design utilizes Xilinx FPGA XC2V1000 and makes it possible for real-time application. |