Research On The Hardware Implementation Technique Of Parallel Genetic Algorithms Based On FPGA

So far, the research on algorithmic implementation of Genetic Algorithms (GAs) still focused on software implementation. However, the software languages are processed with serial at speed. Undoubtedly, it goes against the natural parallelism of GAs. Thus, the real-time implementation of GAs is restricted greatly. As a result, it prohibits the widespread use of GAs. Therefore, the project proposes an implementation technique of parallel GAs based on FPGA device, which uses the individual and its fit degree of the best one to replace the individual and its fit degree of the worst one by their address, thus speed up convergence of Genetic Algorithms (GAs) by means of hardware implementation.Firstly, this thesis analyzed the basic principle and method of GAs and introduced the characteristics and the development process of Field Programmable Gate Array (FPGA) and Hardware Description Language (HDL). Then, according to the characteristics of FPGA and HDL and the function request of GAs, following the top-down design idea, the whole system was divided into some modules and the thesis analyzed function of each module in detail. Finally, using Very High Speed Integrated Circuit Hardware Description Language (VHDL) to program function implementation of each module, all the modules has been analyzed and tested, function simulated, synthesized, placed and routed, timing simulated by Altera Quartus II 8.0 and the hardware test was implemented in the aimed chip EPlC12Q240C8.The results indicated:1. The design which adopted coarse granularity model in parallel methods of GAs has realized basic functions of parallel GAs.2. The speed of operation of the whole hardware system which used pipelined technology has been improved more than the parallel GAs system based on software.3. The project adopted LogicLock optimized technology which made the system allocate the hardware resources properly and improved the working speed and the reliability of the system.4. The design has taken up smaller area of the aimed chip.