With the development of Internet and communication technology, the digital communication system has become more and more complicated, as the result, the importance of developing the universal IP has been obvious.This dissertation focuses on the IP design of CTU (Communication Transition Unit) in a digital communication system, mainly on the design of the interfaces of CTU to UTOPIA3 and CPU. The UTOPIA3 IP is used to receive and transmit the information cells according to the protocol. The CPU Interface is the "bridge" between the CTU and CPU, which pass the configuration information to other modules in CTU, transfer the status information to CPU and test the SSRAM.The main research work of this dissertation is as following:Firstly, two IP logic designs have been accomplished in this dissertation, which are described by Verilog HDL, and based on HLD (High-Level-Design) technique.Secondly, the functional simulations of the IP are completed.Thirdly, these two IP are integrated into the CTU and verified fully based on the FPGA.Lastly, the method of the function simulation is elaborated, especially the Bus Function Model (BFM). |