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Rs Decoding Algorithm, And Rs (256,252) Decoder Realization

Posted on:2003-12-30Degree:MasterType:Thesis
Country:ChinaCandidate:P Z DuFull Text:PDF
GTID:2208360062996232Subject:Computer application technology
Abstract/Summary:PDF Full Text Request
Du Pingzhou (Computer Application)Directed by Prof.Sun HuixianError-correction coding is used widely in satellite communications, mobile communications and data storing. Reed-Solomon code is one of the most useful Error-correction codes, which has been accepted by CCSDS AOS as part of standard protocol. This paper focuses on the algorithm of RS decoder and the implementation of RS(256,252)decoder. RS(256,252)code is extended from RS(255,252)code ,a byte-wide single error-correcting and double-error detecting cyclic block code. Considering RS(256,252)code, its block length n equals to 256 with each block containing 252 8-bit information symbols over the finite field GF(). The number of error symbols that can be corrected by the decoder is 2. The design process includes storing the input data, calculating the syndromes, designing multiplier and divider and solving the key equation. During the course of designing circuit, I use the software Xilinx Foundation 3.1 in the associated manner of VHDL and schematic. Finally, this decoder is implemented by FPGA-XC2S200PQ208C-5. It operates very well at up to 100Mbps with 321 bytes delay. Since this decoder has high error-correcting speed and regular structure, it may apply to data transmission and storage to decrease error rate.
Keywords/Search Tags:RS code, Error-correcting control, Multiplier and divider.
PDF Full Text Request
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