Algorithm Based On Hierarchical Test Of The Functional Modules Of The Large-scale Rtl Combinational Circuit

Reliability of digital systems is more and more important with the wide use of digital computers. For improving the reliability of systems, they all need to be tested in designing, manufacturing, and functioning stages. This dissertation focuses on automatic test generation (ATPG) algorithms for very large-scale integrated circuits at register-transfer-level (RTL).This dissertation designs a data structure, etbl, for RTL circuits for VLSI ATPG. EtbI can conveniently and efficiently access the structure and function information of RTL circuits for ATPG. This dissertation presents a format-transformer, which can transform ISCAS-85 and ISCAS-89 benchmarks verilog HDL descriptions to inner data structure, etbl, applied in RTL ATPG.Based on RTL circuits structure described in etbl, this dissertation presents two hierarchical ATPG algorithms based on structure for RTL combinational circuits. The two algorithms generate tests for RTL circuits by test sets for modules. We apply the two algorithms to generate tests for ISCAS-85 and ISCAS-89 benchmarks. The experimental results illuminate the hierarchical test generation algorithm can greatly decrease the scale of test sets (about 66%), but the fault coverage and time performance are lower than gate-level test generation. The experimental results also testify that the algorithm can decrease test generation complexity and simplify the circuit structure and function information. In addition, the algorithm also enables the possibility for highly efficient parallelATPG.