Energy- and Reliability-Aware Design of High-Speed Global On-Chip Interconnects

With the increase of circuit densities and operating frequencies on-chip interconnect delay, crosstalk noise and energy dissipation have become the dominant factors of performance and signal integrity in deep sub-micrometer (DSM) and nanometer scale VLSI circuits. Faster rise/fall times of the signals, and lower resistance of wider global lines lead to increasing prominence of on-chip inductance and inductive crosstalk effects along with capacitive crosstalk. Therefore, existing coding techniques for capacitive crosstalk and energy reduction in resistive-capacitive (RC) interconnects are not suitable for resistive-inductive-capacitive (RLC) interconnects in high-speed circuits. On-chip interconnects are also susceptible to various other DSM noise sources. Error-correction coding (ECC) improves interconnect-reliability against DSM noise. This work proposes a unified coding approach for addressing crosstalk delay, energy and reliability for on-chip RLC interconnects. Results show that the proposed unified coding approaches achieve up to approximately 20% and 25% reduction in the maximum crosstalk delay and energy dissipation, respectively, with some wiring and area overheads. Besides, ECC makes it possible to transmit low-swing signals to tradeoff energy dissipation with reliability.;This dissertation also investigates the performance of negative capacitance field effect transistor-based drivers for global interconnects in sub-threshold circuits. Negative capacitance (NC) region is obtained in conventional metal-oxide-semiconductor (MOS) structure field-effect transistors (FETs) if the standard insulator is replaced with a ferroelectric insulator of the right thickness. NC enables step-up voltage transformation to amplify the gate voltage, and obtains a steeper sub-threshold slope (S). A driver transistor with small sub-threshold slope (< 60 mV/decade) compared to conventional MOSFET driver transistor provides faster switching with low-power operation which is utilized in driving global interconnects in sub-threshold circuits. A comprehensive study of single-gate NC FET-based global interconnect drivers for sub-threshold circuits based on theoretical principles and simulation are presented in the dissertation.