Design Of LDPC Decoder Based On Parallel Hierarchical Decoding Algorithm

In the1960s, Gallagher propose LDPC codes in his doctoral thesis. Then people start the research for this codes for decades. The decoder design for LDPC code is difficult, and therefore many new decoding algorithms are proposed. Layered decoding algorithm is one of the most important algorithms. The parallel layered decoding algorithm proposed later refined the original layered decoding algorithm. In this paper, the IEEE802.16e LDPC codes is used to the analyze layered decoding algorithm and parallel layered decoding algorithm. A decoder hardware design scheme is proposed for parallel layered decoding algorithm. Puncturing is used to produce arbitrary rate between1/2and1. Hardware implementation results are shown at last. The results show that using matrix of IEEE802.16e LDPC code and TSMC65nm process, the proposed decoder design can achieve a throughput of1.2Gb/s with10iterations. The chip area is about1.1mm2. Puncturing is used in the design to produce arbitrary rate between1/2and1.