Research On The CMP Of Patterned Copper Interconnect Structures With New Diffusion Barriers

Chemical Mechanical Polishing (CMP) has been widely used in VLSI manufacturing. Copper interconnect barriers not only block the copper diffusion into the dielectric, but also improve the adhesion of the copper and dielectric. However, during CMP process, Cu loss may produce due to the different polishing rate of copper and barrier, which will affect the RC delay. CoMo is first investigated in our lab, and is considered as a promising barrier because that it is similar to RuTa in the structure and has lower resistivity to Ru.In this paper, we design and manufacture a CMP test chip to research different copper diffusion barrier performance referring to MIT’854test chip. The test chip contains72different structures, which can be used for surface morphology, resistance test, leakage test and capacitance test. The design and manufacturing of the test chip are introduced in detail in this paper. The diffusion barriers studied in this paper include Ta, Mo and CoMo, which are all30nm.The results of surface morphology structures show that the copper dishing defects are smaller in Ta and CoMo structures. The CoMo structure obtains similar surface smoothness to Ta structure with only one kind of copper polishing slurry, and CoMo structure even has the least surface roughness.The resistance test results show that the copper depths are almost the same in the same area, which means good overall surface flatness. The very small leakage current evidences that the copper and barrier can be removed at the same time with only the copper CMP slurry in CoMo structure.This study shows that the designed and manufactured test chip can be effectively used to characterize the various defects after CMP; the patterned copper interconnect structure with CoMo as barrier obtains comparable surface flatness and even smaller roughness to the structure with Ta as barrier, which is polished by only the acid copper CMP slurry.