Fpga-based Afdx End System Design

AFDX is the information transmitting system of the new generation airplane. The thesis builds a AFDX standard compatible AFDX end system developing platform, which bases on FPGA,To simplify the hardware design, The AFDX end system developing platform uses SOPC, which has a Xilinx Virtex-4 FX12 FPGA as its core. The FPGA embeds a PowerPC 405 and two MACs hardcores. The PowerPC 405 completes in-die computation. Two MACs connect with redundancy AFDX interconnection. CPCI interface is chosen to connect with avionics subsystem.Considering conveniences and flexibility, while complete AFDX protocol, the AFDX specific link layer is divided from other parts. The link layer is implemented by a soft IP core, including integrity checking, redundancy management in receiving processing and traffic regulation, redundancy management in transmitting processing.Considering different end system may use different scheduling algorithm, scheduling module is divided from IP core and implemented by software. Scheduling algorithm is based on weighted fair queuing, adds the consideration of frame transmitting time, overall consideration priority, length, BAG, jitter, schedules the sequence of transmitting.