The Design And Realization Of The Engineering Signal Real-time Wavelet Analysis

Engineering Signal of wavelet analysis was mainly confined to large amounts of data collection with using the software analysis and processing, it can not achieve the requirements of real-time. This paper proposed discrete wavelet transform hardware architecture from the practical point of views. And also it will be achieved in the FPGA.This paper mainly completes work:This paper describes the Mallat algorithm flow chart by the direct-viewing graphic mode which based on deeply analyzing the basic theory and characteristics of wavelet. This algorithm was similar with the filter theory:By repeatedly using high and low pass filters to complete the calculation of wavelet decomposition levels on which I had designed the overall design of the hardware architectureIn this paper I realize the wavelet filter group's design in FPGA based on self-made ARM and FPGA test platform. In order to improve the speed of convolution, this paper adopt the DA distributed algorithm whose advantage was only one lookup table and an accumulator with shift. So it can reduce hardware resource consumption. In order to improve the speed of wavelet analysis, we joined the pipelining technology, optimization of storage structure technology, reduced the critical path technologies and so on.In order to improve the proposed structure of discrete wavelet analysis of the correctness of hardware, I designed a fully integrated RTL-level description though Verilog hardware description language which realized the synthesis and the simulation in ALTERA Corporation's FPGA development software QUARTUS 119.O.We verified the correctness of the hardware structure by comparing the simulation results with the MATLAB software and Modelsim software. It can be achieved on the ALTERA EP3C25 chip devices.Parallel decomposition of data was transferred for ARM's frame buffer at the control of global synchronous clock. This paper provided the Wavelet analysis of the original ECG signal and low-frequency signal decomposition which were showed according to the high 8-bit, low 8-bit comparison from the signal generator.This paper had designed the Sampling and interpolation Computing module so that the results of the waveform was finally closed to the smooth or continuous.The results show that this design works of wavelet analysis for testing the program meet the requirement of low resource hardware consumption, short critical path delay, easily to implement and so on. But the technology had not achieved maturely because the reference were extremely few and our country's research in this domain were just started. Particular parallel architecture system of wavelet need further study in future work practice.