Design And Implementation Of E1/t1 Framer

The emergence and continuous development of the Internet have brought great change in modern communications. This access network technology T1 and E1 was initially used to handle voice communications. So far, it has been able to carry multiple voice, video, data channels, and it has been widely used in the access network data services. Line interface and framer chip is one of the key technologies about T1, E1 access technology. With the rapid development of the communications business and wide application of T1, E1 access technology, the line interface and framer chip applications also will be more extensive. So researching the line interface and framer chip, enhancing its integrated rate of the number and accelerating the speed of frame synchronization is practical and has a bright market prospect.This paper first studies the principle of E1/T1 line interface and framer chip. And then it gives an outline of communications protocol ITU-T G.704 and ITU-T G.706. Some key technology is researched, such as synchronization of all kinds of frames, realizing methods of various alarms, extraction methods of signaling information. On this basis, the framer compatible to the communications protocol ITU-T G.704 and ITU-T G.706 is designed in this paper. And the fast-framing method in T1 framer is studied in detail,then a new T1 framer architecture is designed ,which has the search state machine, state memory, read and write address generator. Using less memory, it reduces the device area, and speeds up the T1 frame synchronization. The entire circuit is achieved in the Verilog hardware description language. The function simulation and FPGA verification for the design have been done. The result shows that the design can operate correctly, which is able to quickly extract the header of frame, achieve frame synchronization, and realize the other additional functions correctly. Then, utilizing the SMIC 0.13μm CMOS technology library and the Synopsys Design Compiler, the design is synthesized. The area is 319590.375μm2, which about 29118 gates, the maximum operating frequency is about 65.536MHz. Finally, test after fabrication shows that the design in this paper is correct and feasible.