Design And FPGA Implementation Of Multi-mode Frame Synchronization For DVB-S2X

In recent years,satellite communication technology has developed rapidly in the direction of high throughput,terminal miniaturization and mobility.The new generation of DVB-S2 X standard has attracted wide attention,because of its advantages such as high bandwidth utilization,wide channel frequency band,large amount of transmission information and strong transmission capacity.The DVB-S2 X standard can support a variety of modulation and coding methods,Very Low Signal-to-Noise Ratio and Super Frame,so as to meet the transmission needs of high-throughput satellite and small mobile terminals.For different application scenarios,the DVB-S2 X standard defines standard frame structure that supports continuous systems and Super Frame structure that supports burst systems.For these two different structures,this paper studies the frame synchronization algorithms and algorithms applicable to continuous systems and burst systems.Its FPGA design and implementation,the main achievements are as follows:1)This paper investigates the frame synchronization algorithms suitable for DVB-S2 X continuous system.Firstly,the existing algorithms are divided into two parts: using the fixed sequence and using the entire frame header sequence of the DVB-S2 X system.The implementation principles,advantages and disadvantages of the algorithms are analyzed.Based on the entire frame header sequence,two improved algorithm are proposed.The first proposed algorithm is to optimize the energy correction term,which can reduce the problem of large correlation peak fluctuations and improve the detection performance.The second proposed algorithm is a weighted frame synchronization algorithm,which can obtain better performance when the system frequency offset is small.The simulation results show that the proposed algorithm can obtain better detection performance with lower implementation complexity under the same channel environment.For high-throughput satellite communication systems,this paper adopts a weighted detection algorithm based on the entire frame header,designs a parallel frame synchronization hardware implementation scheme,introduces the implementation principles of each module in detail,and adopts a peak detection method combining dynamic threshold and multi-peak decision,which can improve the detection probability of the algorithm effectively.2)This paper studies the burst system frame synchronization algorithm.According to whether the synchronization sequence is used,this paper introduces the data-assisted frame synchronization algorithm and the non-data-assisted frame synchronization algorithm,and then proposes a weighted difference based on the differential correlation algorithm.This algorithm makes full use of the low complexity of hard decision,and can further improve the correlation peak on the basis of the original correlation algorithm.The simulation results show that the proposed algorithm can effectively improve the detection performance of the algorithm when the length of the synchronization sequence is different.Based on the weighted differential correlation method,this paper designs and completes a general frame synchronization hardware implementation scheme,which can configure the synchronization sequence length(16～1024)and content according to the system parameters,so that the frame synchronization module has a certain versatility.The length of the synchronization sequence is different,and the resources occupied are also different,so as to minimize the resource occupancy.Comprehensive analysis shows that the module can support system clock frequency up to 200 MHz.