Optimization Of Codec Based On H.264/avc And Vlsi Implementation Of Dpb Management

H.264/AVC, the result of the collaboration between the ITU-T Video Coding Experts Group and ISO/IEC Moving Picture Experts Group, is the latest standard for video coding. It has gained a lot of attention for its enhanced compression efficiency, network friendlyvideo representation and wide target application. A multimedia processor is a chip with the ability to process multimedia data efficiently. To satisfy the high throughput and real-time requirement of video application, multimedia processor must have the features of excellent performance, low power consumption and also low cost. Multimedia processor now plays a very important role in consume electronics, such as HDTV, DVD player, video phone. Thanks to the rapid development of VLSI technology, we now can put more transistors on the same die size. SoC become a good candidate of the implementation for multimedia processor. Since the new standard is just at its beginning, it's definitely worth studying the SoC solution of H.264/AVC.This paper is a summary of studying on H.264/AVC video coding theory and what the author have done in the H.264 CODEC SoC design projects. The paper is written according to ASIC/SoC front design flow and the content mainly include algorithm complexity analysis and optimization, SW/HW partition, system architecture design, DPB management module design and FPGA prototype.In the aspect of H.264 Encoder, we introduce the complexity and the methods of optimizing Encoder, including improve the calculation of SATD using Intel SSE2.Because of the optimization, the speed of Encoder is twice as fast as before. As for Decoder, we introduce a method for optimizing DPB management, and implement it with HW & SW, which makes the memory reduced at least one half compared with the former size. At last, we present FPGA prototype verification.Finally, chapter 6 concludes this paper and the problems requiring further studies are discussed.