Electronic Parking Fee System Baseband Circuit Design And Implementation

Traffic pressure increases as the development of road traffic in recent years. The system of Electronic Toll Collection (ETC) which can obviously reduce the charge time has become the most effective method to solve this problem. Baseband circuit, as an important part of ETC system, has been applied to connect CPU and RF unit, including HDLC, FMO encoding/decoding and intelligent power management for OBE. On the one hand, it completed data processing from CPU; on the other hand, it completed data processing from RF uint.In order to regulate the design and improve system compatibility, china has announced national standards named Electronic Toll Collection--Dedicated Short Range Communication. Physical layer and datalink layer of DSRC (Dedicated Short Range Communication) which are relative to baseband circuit has been analyzed in this paper. The baseband circuit has been designed based on DSRC.HDLC has been designed based on Wishbone bus, using 'top to down'method. First, figure out top layer framework according the requirement, then divide the complex module into submodules and finish the program code by using Verilog HDL. For FMO, it has been designed in schematic method according to encoding/decoding rules.Finally, after synthesize and simulation, the code has been downloaded to FPGA, and then complete the waveform testing and validating. Sleep mode and active mode has been proposed for power management. Besides, module classification and time division has been used in order to reduce the power consumption of the system. At last, Protel schematic file and PCB file have been designed and software/hardware debugging of the circuit has been completed.