Fpga Hdlc Controller Pcicore-based

The HDLC controller with PCI local bus interface is widely used, but this kind of ASIC chip have mang problem, such as the FIFO overflow in the high data stream and initialization transmission channel time succession mistake, so on. Moreover the chip edition unceasingly promotes, project is out of control, the manpower remain invests, it not only causes the difficulty to the equipment, also causes the equipment unceasingly to encounter the question in the operation, it needs to invest the massive manpower and resource maintenance after the production is producted in the large scale, Therefore it has the practical significance to study the based on the PCI core HDLC controller, the network interface is CE1.This article has referred to the CN8474 design method, thoroughly has analyzed the demand definition function, has absorbed the massive similar topics experience, proposed to realize all functions and to solve ASIC's bug. Based on the FPGA's function and performance, it make the innovation and the exploration research to use FPGA to replace ASIC. The main content is:1. It has analyzed the closed the partial of the PCI and the HDL;2. It detailedly introduced the FPGA realization function and each sub- module function, the DB definition, receiving and transmiting the data, the channel starts and stops in brief.3. It detailedly described the FPGA's framework, all sub- module definition and detailed mechanism. It described the PCI controller with emphasis, the DMA controller, the HDLC controller signal definition.4. It detailedly described the verification environment, through testing environment designed to meet the scheduled inspection requirements, the design has been applied to the product.