Design And Implementation Of The Frequency Synthesizer In An Infrared Image Processing Chip

Infrared imaging has many advantages,like long distance working range, anti-interference, good smoke or fog penetrating ability, can be work all-weather and day-time, etc. In military and civilian areas it has been widely used. The value of the final imaging system depends on whether you can extract and use the image information adequately. This paper has designed a frequency synthesizer which is used in a SOC-based technical architecture of infrared imaging processing chip, as a key module, it provides the clock which is used to get information from IRFPA.In this paper, firstly according to the working principle of the phase-locked frequency synthesizer, it models and analyses the synthesizer's architecture and various modules, and on this basis designs the system and optimizes the circuit's parameters. Then it analyzes the system's noise sources and proposes how to reduce the noise of the voltage-controlled oscillators.Next, according to the system's function and performance which required by the the infrared image processing chip, it designs the frequency synthesizer architecture, which uses input divider, output divider and programmable frequency divider to achieve the frequency digitally programmable adjustmen; Furthermore, uses frequency synthesizer's two output clock and the D flip-flop delay to achieve the phase shift. The specific circuit implementation as followes: uses delay unit of the PFD to eliminate the dead zone; uses differential structure's charge pump, dual-loop structure's filter and the differential signal-controlled voltage-controlled oscillator to reduce oscillation control signal noise as much as possible, by using this method it optimizes the performance of the output clock; uses incremental charging capacitor according to the growing of divider factor, the lock detection circuit can ensure the lock detection output signal to be reliable and accurate.Finally, under the GSMC 0.18μm 1P5M CMOS mixed-signal process, the paper plots the individual modules and the overall simulation waveforms and layouts. Finally the frequency synthesizer's output clock has achieved 2MHz-13.5MHz whose step is 1/16MHz for the unit to change, and be able to achieve 1/16 cycle steps for phase shift. Under the typical situation environment that is TT, 1.8V supply voltage, 25℃, when the output clock'frequency is 3MHz, its peak to peak jitter is 200ps, which achieved a low jitter.