Data Acquisition And Compression System Design Based On FPGA

In some serious tests and experiments, rigorous requirements have been demanded, which are not only the characters of small capacity and low consumption, but also the function of recording a large quantity of datas. This article has proposed that compressing test datas on the spot by using FPGA to solve the problem. In order to further decrease the capacity and the consumption of the circuit, we supposed that putting the controlling circuit of data acquisition in the test system into the FPGA plan, so this can realize the integration design of data acquisition and data compress.In the first part of the article, we introduced the relative basic knowledge of FPGA, FPGA platform and the corresponding software development environment. On the basis of that we made the paper on FPGA design development.According to the characters and requirements of modern test system, during the part of the data acquisition, we use FPGA to realize the control of A/D converter AD7492, and the negative skewed technology,internal trigger and external trigger programmable controlling technology, also made high frequency noise filter operation on acquisition data by using the method of moving filter. By setting the trigger method and the trigger threshold on the trigger module, it can meet the needs of most of the test environment.During the part of the data compression, firstly introduced the relative compression theory, after comparing and analyzing the relative merits of several lossless compression algorithm, we selected the lossless compression algorithm—LZW which can easily be realized on hardware, and analyzing the detailed implementation procedure of the algorithm both from the software and the hardware. During the software implementation procedure, we introduced the two important technology which are dictionary updating strategy and fast finding dictionary contents ,and it has supported good module for hardware realizing. While during the hardware implementation, we made our focus on detailed design of important module and the ultimate design results, at the same time we also introduced the design results of accessory module. At last, by setting up test platform to verify system both from the function and the performance. Lots of tests have made clear that working steadily of the system, fast compression speed (above the 8MByte/s ), good effect on data compress(about 25%),and low working electric current(37mA) to realize the integration of three of speed, performance and consumption.The initial design ideas has been achieved.