The Research And Design Of USB Host Controller IP Core

Universal Serial Bus is a kind of communication interface standard with plug and play, high scalability, high-speed stability, etc. Current PC-based USB applications tend to be mature, but some portable USB devices require being away from the PC for data communication. Therefore, it is increasingly important to apply USB host controller in embedded systems and achieve point to point USB communications. This study aims to develop a USB host controller IP Core support that can be used in embedded SOPC system.This article employs the idea of top-down design to conduct the top-level design of USB host controller IP core and module division on the basis of in-depth studies about the USB protocol specification and the OHCI host controller specification. Finally this study aims to complete the RTL-level description, simulation and verification of USB host controller IP core, and finally carry out the analysis of the simulation and synthesis results. This article includes the following aspects:First of all, this article carries out in-depth studies about the USB protocol, and then conducts the top-level design of USB host controller IP core and module division on the basis of in-depth understanding of USB protocol.Secondly, this study employs integrated RTL Verilog HDL hardware description language to design functional sub-modules, host control module, serial interface engine, Avalon bus interface module, receive and send buffer, etc. USB host takes the core function of controlling module to complete the data transmission, and serial interface engine takes the function of the USB protocol layer. These two modules are the most critical parts of the host controller IP core. Avalon bus interface layer with the send and receive buffer modules achieves the function of clock domain switching and asynchronous data transmission in time domain of the system bus and USB bus. This design adopts a new parallel algorithm for CRC check and finally it's proved that it improves the efficiency of verification, optimizes the timing characteristics of logic circuits. And it incorporates the design of FIFO memory whose depth can be configured as data sending and receiving buffer. It is finally conducive to users'clip for the sake of saving logic resources on the basis of guaranteeing the rate of data transmission.Finally, it draws up detailed simulation test program for the USB host controller IP core, composes structured testbench files, and carries out functional simulation towards sub-modules through professional simulation tool-ModelSim in order to ensure that logic functions of the module meet the requirements of the design. Then, it executes the logic synthesis and downloading verification for the host controller IP core through the Altera FPGA platform in order to understand the logic consumption and its timing characteristics.Through the thorough analysis of the simulation and test results of USB host controller IP core, it's indicated that each module of IP core logic functions meets requirements of the design, and the host controller can successfully accomplish the task of sending the assigned data package in the patterns of both low speed and full speed specified in the USB1.1 protocol. This design provides feasible and effective implementations for embedding USB host controller in the SOPC system, expands the peripheral interfaces of SOPC system. It is of higher application value.