Low-power Delta-Sigma Modulator With Time-division Technique

Analog-to-Digital Converters (ADC) play a very important role in digital signal process. The ADC's precision has been greatly concerned in many kinds of high resolution.Δ-∑modulator based on ADC technology can reach a high resolution over 16 bits, it is the most popular converter for high resolution applications. Currently, low powerΔ-∑modulator is a hotspot.Recently, in the typicalΔ-∑modulator architecture, most of the integrator shift states between'busy phase'and'idle phase'in one period, thus the integrator efficiency is only 50 percent. In this thesis, the typicalΔ-∑modulator architecture is analyzed, and the Time-Division integrator technique is proposed, which can replace the integrator in'busy phase'in the entire period. For an even order modulator, only N/2 integrator can reach the N-order modulator. The architecture reduces the power consumption and chip area effectively. In this thesis, a behave model for Time-Division modulator is built by simulinkTM, and the difference between Time-DivisionΔ-∑modulator and traditionΔ-∑modulator is analyzed, such as power consumption, noise and critical components.A Second-Order Time-DivisionΔ-∑modulator is fabricated in 0.5μm process. In order to appliance in low power field, the circuit introduces some special module, for example: a double loop relex clock generator, a Two-Stage Class A/AB OP-AMP. In order to get high resolution, the voltage source and the current source also comes form bandgap whitch. The modulator operates at 5MHz, while the input signal is 20 kHz (OSR=128), the SNDR is 65.5dB, the DR is 70dB, and average power consumption is 3.8mW. The simulation result indicates that the Time-DivisionΔ-∑modulator can reduce 10% power consumption relative to the tradition typical architecture, and the performance is remained.