Research And Implementation Of Turbo Encoding And Decoding Scheme

Turbo channel coding and decoding technology has been discovered since 1993 and caused widespread concern in the industry.It also has been applied in many communication systems for its excellent error correction performance.This paper studies how to combine the Turbo code with the constant-weight code to realize the brightness adjustment in the D-VLC system,the parallel interleaver implementation scheme in turbo code,the parallel decoding scheme and the design and implementation of parallel decoding algorithm.The main work of the paper is as follows:Firstly,we propose a scheme to adjust the brightness of D-VLC system by combining Turbo code with constant-weight code.On the basis of using Reed-Muller and turbo code to adjust the brightness in D-VLC system,we combine turbo code with constant-weight code to adjust the brightness.This scheme will use constant-weight code which its code weight is consistent with brightness level to re-encode the bitstream which is punctured,and no compensation symbols in this scheme makes the transmission efficiency improved.The simulation results show that the proposed scheme in this paper increases the decoding complexity,but reduces the bit error rate and increases the brightness range.Secondly,two new parallel interleaver designing schemes for turbo code are proposed.The first parallel interleaver is generated by adding the code matching and S stochastic constraints in the time and spatial permutation(TSP)interleaver.This interleaver increases the free distance of the turbo code and improves the decoding performance.The simulation results indicates that the interleaver can achieve better decoding performance than QPP interleaver at some encoding length.The second parallel interleaver is formed by using the relative prime(RP)criterion in TSP interleaver.The interleaver uses the RP criterion in temporal permutation and the random RP criterion in spatial permutation respectively.This method is simple and reduces the storage required by the hardware implementation.The simulation results show that this interleaver has a better decoding performance than the QPP interleaver after simple filtering.Thirdly,an improved parallel decoding architecture-window parallel decoding architecture is proposed based on the full parallel turbo decoding architecture.This decoding architecture combines the traditional sliding window method with the full parallel decoding architecture.A fixed length code word is processed by a decoding unit and these neighboring decoding units provide information to each other.The simulation results indicate that this new architecture improves the bit error rate performance by 0.2dB than the full parallel decoding architecture.In addition,an improved scheme of Log-MAP algorithm in turbo decoding is proposed.The scheme reduced the calculation error by considering the dynamic range of data and the simulation results show that this new scheme improves the decoding performance.Fourthly,the FPGA implementation of the parallel encoder and decoder based on the window parallel decoding architecture is introduced and the main content is as follows:the design of parallel turbo encoder and interleaver,the selection of the bit width in the parallel decoder and the realization of the intermediate calculation unit module,the parallel QPP interleaver module and the decoding module.