Research Of EG_LDPC And Implementation On FPGA

The Low Density Parity-Check (LDPC) code was first proposed by Gallager in 1962, of which the research had been halted due to constraint of the technology development in the following more than 30 years. In the 1990s, Mackay and Neal found that LDPC is one kind of good codes as well as turbo and near to Shannon limit. Based on this discovery, the research about LDPC has grown and got a big development in the past several years.Based upon Euclidean Geometry, Cyclic codes and linear block codes scheme, this dissertation is trying to research on LDPC and presenting a proposal, for how to implement the LDPC encoder on hardware according to DVB-S2 standard. The details are as below:1. The structure method of LDPC parity check matrix has been studied in detail, as well as belief-propagation decoding algorithms, general encoding and fast encoding algorithms. Euclidean geometry LDPC and encoding algorithms based on the parity check matrix are mainly researched.2. A new method for constructing the first class 2-dimention (2,0,s) order EG-LDPC is presented; and a new method for getting generated polynomial from parity check matrix of cyclic EG-LDPC by simple calculation is proposed.3. A method for constructing the first class multi-dimension (m,0 s) order cyclic EG-LDPC is presented; and an implementation of non binary LDPC encoding from QC-LDPC is proposed, with the hardware encoder circuit introduced.4. On the question that the complexity and the quadratic of code length are proportional by general algorithms, the fast encoding method of LDPC is mainly studied. An encoder is presented on FPGA with hardware language according to DVB-S2 standard. The LDPC parity check matrix in DVB-S2 standard is irregular and is composed of one sparse matrix and one double diagonal matrix and has condition to be encoded directly in linear time. By corrective method of accumulation to replace multiply operation, the proposal gives a method to save memory space.