| LDPC codes are a kind of linear block codes defined by its check matrix. Theperformance of LDPC codes under belief propagation decoding algorithm can approachthe Shannon limits. The iterative decoding algorithms of LDPC codes are of theadvantage of linear complexity and convenient for parallel implementation, which makeit be researched widely. Inspired by the iterative decoding algorithms of LDPC codesand turbo codes, the idea of iteration is applied to various aspects in communication,and a plentiful of achievements have been obtained. This dissertation is concentrated onthe encoding and decoding algorithms for LDPC codes and the applications of iterativealgorithm in channel equalization. The contents of this dissertation are lined below:First, a quasi-parallel LDPC encoding algorithm using recursion from both sides ofthe parity-check bits is proposed, and the FPGA implementation scheme of it is alsoproposed. The implementation result shows that the encoder can realize a quasi-paralledencoding of LDPC codes under linear resource consumption.Then, an implementing scheme of sum-product algorithm is proposed based ontwo-dimension broken line approach, which avoids the look-up table with size related tothe exponential of the number of quantization bits and reduces the memory consumptionof the decoder. Then, an algorithm called second-minimum value corrected min-sumalgorithm is proposed based on the implementing scheme proposed above. Thealgorithm uses three two-dimension broken line approach to correct the minimum valueand its performance is very close to that of the floating point sum-product algorithm.The correction process of this algorithm just includes simple arithmetic and logicoperations, which is easy to be implemented on FPGA.Afterwards, a serial concatenated order statistic decoding (OSD) algorithm withthreshold is proposed for LDPC codes with short or moderate code length. Theproposed algorithm possesses a significant gain over conventional concatenateddecoding algorithms. The problem for the FPGA implementation of the OSD algorithmis discussed, and a Gaussian elimination structure based on RAM is proposed, which isapplied in the FPGA implementation of OSD algorithm. The result of simulation andimplementation proves the validity of our scheme.A block turbo equalization algorithm is proposed, which is generalized from DataDirected Estimation (DDE). The convergence rate of our block turbo equalizationalgorithm is faster than that of the linear MMSE turbo equalizations. Two simplifiedschemes of this block turbo equalization algorithm is also introduced. The two simplified schemes include LC-TDDE algorithm and BSIC algorithm. The LC-TDDEalgorithm performance better than linear MMSE algorithm, while its complexity isproportional to the square of the length of data block; the BSIC algorithm possesses alinear complexity with the length of data block with a performance very close to thelinear MMSE algorithms. For high order modulation, a simplified demapping algorithmbased on hard information feedback is used, which reduces the complexity of thedemapping process. The performance of this simplified algorithm is close to the originalsoft demapping algorithm. Consequently, the proposed block turbo equalizationalgorithms with LDPC codes are implemented in a High Frequency data communicationsystem, obtaining a performance more than3dB over the conventional systems.Finally, a efficient pilot pattern based on single time-frequency chucks is proposedfor OFDM systems. An iterative channel estimation algorithm with LDPC codes as itschannel coding scheme is proposed for this pilot pattern. The iterative channelestimation algorithm uses a channel estimation algorithm with two-dimensioninterpolation algorithm based on weighted generalized inverse matrix as its initialestimation. The iterative channel estimation algorithm improves the problem that theaccuracy of channel estimation is sensitive to the velocity of the receiver under thecondition of lack of pilot symbols. |
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