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Research And Implement Of Multiprocessor Clock Synchronization Technology

Posted on:2011-11-29Degree:MasterType:Thesis
Country:ChinaCandidate:S H YouFull Text:PDF
GTID:2178360305995223Subject:Control theory and control engineering
Abstract/Summary:PDF Full Text Request
The aircraft pylon test system can detect and analyze the quality and performance of the aircraft pylon through examination and controlment to the aircraft pylon system.In previous, the. single-processor test method was adopted to analyze the performance of the aircraft pylon system. Because only one processor was adoptted to process signals in this method, the system efficiency and system accuracy can not meet to the complexity and accuracy requirements of the current testing system. In order to deal with the problem, the multi-processor parallel processing method was applied in this paper. Meanwhile, Ethernet communication protocol was adoptted between the processors. Because of the processors have their own clock references, the clock synchronization technology was needed to provide a precise clock to the aircraft pylon test system. The purpose of this paper is to provide a method to solve the synchronization problem of the processors.The advantages and disadvantages of the current clock synchronization methods were analyzed. The principle of the IEEE 1588 clock synchronization protocol was researched. The reasons of the error were analyzed. At last, a clock synchronization method was designed. In this method, the hubs with smaller delay were emploied as network bridge device. In order to improve the accuracy of the time stamp, the time division multiplexing (TDM) technology was applied to control the network flow and the position of the time stamp was located to the MⅡlayer. At last, a test platform on which the clock synchronization protocol was realized was setted up, the synchronization error can be less than 10μs. The innovation of this clock synchronization method was to use C8051F040 instead of FPGA as the hardware to achieve time stamp during the message transmission and provide the precise frequency adjustable clock. Compared with the traditional method with FPGA, the proposed method can reduce the exploitation difficulty and workload. It can resolve the clock synchronism problem for aircraft pylon in theory, and can be as a foundation for follow-up work. This issue's results have certain extension values, and can be applied to other related platforms after simple changeing.
Keywords/Search Tags:Ethernet, clock synchronization, ARM9, delay, Multiprocessor
PDF Full Text Request
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