Design And Implementation Of Radar Signal Processing IP Core Based On FPGA

With increasing development of radar signal processing technology, it is becoming very important to attach the significance to universal, systematic and modular design standards, and a possibility with the development of FPGA and reusable IP core technique. IP core development is presented in three aspects. First, radar signal processing IP core is realized by using the hardware descriptive language; and then, based on the SOPC design idea and combined with the embedded proccesor PowerPC provided by FPGA, integrated real-time signal processing equipment is achieved; finally, the System Generator tools afforded by Xilinx company contributes to a rather convenient system design. The emphasis of this paper is the design of radar signal processing IP cores.Combined with the flow of signal processing of the pulse compression doppler radar, this paper design and implement algorithms for adaptive beamforming, digital down conversion and pulse compression. The adaptive beamforming modular is designed by using float-point systolic array structure realized in two parts: one is the achievement of the custom floating-point format and the floating-point algorithm unit; the other is the improvement on the existing systolic array structure with the implementation on hardware.Combined with the project-specific requirement, digital down conversion module mainly contains the low-pass implementation, and a relatively novel method is raised in this paper for filter realization. The simulation of pulse compression algorithm and the realization of the method both in time domain and frequency domain are also respectively given.