White LED-driver IC Design Based On ASIC

With the development of semiconductor technology, to achieve higher performance requirements, more and more IC design needs digital circuits and analog circuits integrated on one chip. According to the traditional digital circuit design method, it commonly used HDL languages behavior of the system-level circuit description and schematic descriptions play the same effect. Then through functional verification, logic synthesis and optimization, a reasonable inference circuit structure, and according to the layout design of circuit schematic, finally annotate back the information including layout parasitic to DC.With the simulation result of mixed circuit, if the post-layout simulation results perfect, we can tap-out. In recent years, with the high-speed development of ASIC, FPGA design, EDA technology, the physical-level digital circuit provides a good basis to achieve. ASIC chip design is a multi-application of algorithm, communication protocols, HDL. Compared with the traditional IC, application-specific IC has the advantages of higher processing performance, higher speed, smaller size, cheaper. It plays a good strategic role to links the ASIC and white LED driver IC design.ASIC is to meet specific requirements or for a specific electronic system application. It can be divided into full-custom and half-custom type. Full custom chip (Full-Custom IC) layout are all designed by the user, manufacturer only need to printed the layout on the chip, this method for the users is the most flexible, users can control the circuit parameters, and the only constraint is the manufacturers of process conditions. Half-custom IC using a standard cell library of the components provided by the manufacturer. Library includes gates, flip-flops, RAM, and larger modules. Designers combined these elements to achieve the functions they need. This semi-custom design style provides the flexibility depends on the manufacturer's standard cell library. ASIC is characterized by users targeted in mass production with lower power consumption than general-purpose integrated circuits, smaller, increase performance and reliability, security enhancements, cost reduction and so on. The increasing scale of digital circuits, using traditional methods to design the whole system is very difficult. We usually take the top-down method, the realization of bottom-up ideas to complete the realization of a digital circuit. Top-down design is that a large-scale digital system functionally divided into several sub-module level, these sub-modules are functionally disjoint, and they need to function according to the specific re-divided into a second sub-module, the same, and so on dividing until it is easier to achieve the module.Chip design begins with the concept from the idea of the market, based on these ideas, and then comes to regulate electrical properties and structure. Standard definition of the structure functions of the chips, and one of these functions into one capable of handling the module; electrical properties to the module specification defines the relationship between the timing of information through these relationships are determined. How do we abstract plan into a production value of the territory, first of all to use hardware description language to encode the functions of the design, register transfer level code reflect structural elements and connections between them, it used to describe the design features and can be integrated into a structure similar to the circuit netlist, synthesis process is associated with the technology library, the code is mapped into a cell library component inferred by the synthesis tool to connect them. RTL-level logic synthesis is described by the process of gate-level netlist, which is a translation, optimization and mapping process, and integrated by the EDA tool vendor's main Synopsys Design Compiler, Cadence's Build Gates and MAGMA's RTL Blaster. The design using Design Compiler (DC) as a comprehensive tool, DC read the design of RTL code and in accordance with the timing constraints, synthesis into the structure level, resulting in a mapped of the gate-level netlist.Logic synthesis is driven by various constraints, these constraints include the work environment, delay time, size, power consumption restrictions, etc. The ultimate goal is to produce integrated to meet the constraints of the gate-level netlist. This process the most important constraint focused on time constraints and the size constraints. In addition to disciplining, the need to define synthetic environment file, the file description of process cell library and DC used in the synthesis of other related information. Synthesis tools typically use scripts to control the synthesis process, the script program contains a circuit and timing characteristics of the physical constraints. If the clock signal characteristics (period, phase, duty cycle), reset signal characteristics, the input signal drive capability, the load characteristics of the output signal, input and output timing requirements, and false path identification, these constraints is critical when mapped to RTL code meet the performance requirements of the gate-level netlist.After the logic synthesis is completed, we need to post through an integrated network of tables, based on standard cell library will be obtained after mapping the cell placed in the appropriate position (layout), and through the completion of a complete linear, very delicate territory. We use Synopsys Inc. Astro automatic placement and routing tools to automate the transition from schematic to layout design. Layout refers to the circuit layout design or chip layout, the current chip design process, to include route planning and layout of the entire physical design process, called layout. Clock tree synthesis (CTS) needs immediately after the unit layout, and wiring in these units completed. The quality of the clock tree and chip timing closure is closely related to it as a common clock to achieve the program can easily be integrated into the ASIC design processes. Synthesis and optimization are the use of lines containing the model, the line containing the model is estimated based on statistical estimates of the final wiring capacitance, which has the statistical properties; through post-layout delay information closer to the true value, we need to map a database of these value extracted from the anti-tagging will be timing analysis tool to further optimize the design. Post-layout optimization can only be carried out in DC, so the data need to be anti-marked territory to the DC.This design mainly based on the I2C interface circuit, voltage comparator, add and subtract counter, voltage current converter module. When the circuit in the bus control mode, the transmission of data from the SDA pulse duty cycle control, can achieve 256 levels of brightness control. When the circuit works in the PWM mode, IN1 and IN2 of the level control to enable the state of the module, when the IN1 and IN2 are not simultaneously zero, the PWM circuit adjustment mode. The initial moment, the output voltage Vout is too small, so that fail LED turn-on voltage, feedback voltage is zero, voltage comparator and the output converter is high, so modified counter is set, the output data for the four-bit is 0100, the duty cycle control signal corresponding to 25% and remain unchanged. When the output voltage increases enough to make the LED turns on, the feedback voltage is positive, the voltage/current converter output is high, then add and subtract counter working in the intensive mode, the output gradually from 0000 to 1010, corresponding into a 62.5% maximum duty cycle. When the output voltage reaches the rated voltage, the comparator output is a low voltage signal, then addition and subtraction calculator work in reducing mode, the output of the four data from the 1010 reduced to 0011, corresponding to the minimum duty cycle is 18.75%, which makes the output voltage decreased, at this time the output voltage comparator has become back to high, the counter back to work in the intensive mode, so with the cycle, making white LED's brightness remains constant.