Viscoelastic Fracture Research Of Flip Chip

The invention of transistors and integrated circuits makes electronic products be smaller and smaller in size, and have more and more functions for application. The effective performance of integrated circuit (IC) chips requires the electronic packaging technology to supply the functions of the interconnection of electric signal, mechanical support, the protection of environmental infraction, and the dispersion of heat. Flip chip technology has taken a revolutionary progress of packaging. It has the advantage of its excellent characters such as higher packaging precision, smaller module volume, higher I/O density and shorter distance interconnection. But there are lots of problems during flip chip packaging procedure, such as the interface delamination between die and underfill, the filling vacancy of underfill, the underfill crack, and the accumulated creep cracking of solder joints or underfill during the temperature cycling etc. Experiment and/or test are not the most effective way to finding and solving those issues quickly. The finite element numerical simulation become one of the best way to study the flip chip fracture problem, understand the crack expansion mechanism, optimaize the package design, and improve its reliability.Employment of different material models will directly influence on numerical simulation results. The early studies usually described the underfill materials as classical linear elasticity in order to get a better computational efficiency. But the underfill shows significant viscoelasticity actually. In this thesis, the main purpose is to investigate the effect of viscoelastic underfill on crack of die/underfill in flip chip packaging. Anand model of viscoplasticity is used to describe the viscoplastic mechanical behavior of 96.5Sn3.5Ag solder. The classical linear elastic model and the Maxwell's viscoelastic model are used to describe the mechanical behavior of underfill separately for comparison. Chip and substrate materials are simplified as an elastic model. The three dimensional finite element model with different initial pre-crack of flip chip package is established directly by ANSYS, famous commercial engineering analysis software. At first, by using the finite element software, the welding and curing processes of packaging, as well as the storing process in a dry environment at room temperature after packaging are simulated and analyzed. The effects of the nonlinear viscous process and the different initial crack length on the chip fracture characteristics are discussed.The numerical simulation results give some following conclusions. First, for an interfacial delamination between die and underfill at the chip corner with an interfacial plane straight crack, the fracture propagated from the inner crack circumference is governed by the interfacial shear stress, which is of mode II. The fracture propageted from the chip edge crack tip is governed by the both interfacial shear stress and normal stress, which is of mixed mode I and mode II. Otherwise, when the crack length increases, the distance from the front of crack circumference to the opposite chip corner will reduce, which will lead to decrease the chip temperature deformation and stress intensity factor at the front of crack circumference since CTE mismatch between die and underfill. This decrement partially offsets the increment of stress intensity factor since the initial crack length grows. So the effect of initial crack length growth on the stress intensity factor is not obvious. Consequently, the main reason of the interfacial delamination fracture is due to fatigue deformation and strain accumulation resulted in cyclical temperature change, and is not due to the direct contribution of temperature load inpackaging procedure. Finally, viscosities of the chip solders and undefills lead to the relaxation of the chip stresses obviously. The magnitude of stress relaxation is large. The stress intensity factor decreases significantly at the front of crack circumference, especially at the chip edge crack tip. The simulation based on the traditional linear elastic model of solders and underfill is not only unable to describe significant effect of stress relaxation, but also over-estimates the chip stress level seriously.