| AVS Standard (Audio Video Coding Standard) is a new generation of digital audio and video codec standard, which is formulated in China with intellectual property. The second part of the AVS standard-video coding standard is mainly for high-definition digital television and high-density storage media applications.As the International Telecommunication Union (ITU) Meeting formally adopted AVS standard as one of the four international audio and video codec standard, developing high-quality decoder chip based on AVS standards has become the common focus in the industry.This subject is part of the project-"AVS Application Specific Decoder",which is supported by the Special Fund of Shandong Province Information Industry Development Foundation. According to specific requirements of AVS video decoder chip,the main task is to design and optimize the processor and peripheral modules,and to complete the design, verification, synthesis, static timing analysis and formal verification for the control module in AVS video decoder chip.Firstly, after studying the AVS video codec algorithm and comparing the CPU commonly used in SoC, this thesis selectes the RISC soft core-OpenRISC1200 microprocessor,whose source code is entirely open and free,to develope the control module in AVS video decoder chip. Secondly,,based on improving the control function in AVS video decoder, this paper conductes a reasonable allocation on the internal unit in OpenRISC1200, so as to make it more efficiently complete system scheduling tasks in AVS decoding. Thirdly, according to the requirements of the system expansion, this paper designes the CPU peripheral interface module's IP cores, and integrates SDRAM memory in the chip, so as to enhance the universality of the design, and to improve the integration of chips. This paper introduces each module's detail structure, specific design and the simulation results. After the system integration, while considering the area, speed and power consumption and other factors, this paper writes tcl scripts, and then synthesis and optimize the top-level design using the method of top-down. Morever, we get the timing convergence netlists. Finally, the design is validated, by doing the static timing analysis and formal verification. Necessary results are output.Test results show that the AVS video decoder chip control module has achieved our expected requirement. |
