Automatic Pipeline Generation For Prototyping Verification

With the rapid progress in LSI process, we can integrate a large system on one LSI chip. Verification of a large system is time consuming, and takes more than 60% of the total design time. To reduce the verification period, the functional test using FPGA prototyping is widely used, but the speed is not enough for large systems. In this thesis, we propose a new approach for the acceleration of circuits by automatically generating pipeline structure. In the method, inputs are the FPGA mapping results, and the LUT based circuits are converted to pipeline structure to improve the performance. Note that the method will divide combinational part of a circuit into two or more parts with shorter delay, and the highest frequency will increase. By executing the circuit using the pipelined way, the data throughput of the circuit can be improved. We also devise the resource reduction method in the pipeline circuit generation based on the property of LUT's or logic elements of FPGA. We devised a cut-set based algorithm to divide the circuits into two or more parts, and discuss some conditions for correct pipeline behavior.