The Design Of High Speed, Low-voltage And Low-consumption CMOS/BiCMOS Operational Amplifiers

In recent years,more and more electron with battery supply are widely used, which cries for adopting low voltage analog circuits to reduce power consumption, low voltage,low power analog circuit design techniques are becoming research hotspot.In the analog IC,one of the typical circuits is operational amplifier.Therefore, the design of low-voltage and low-voltage operational amplifier is very necessary. While realizing low-voltage and low-power,it must be noticed for the implementing of the main function of the circuit.Because the low supply voltage affects performances of circuits,it is not very good for just implementing low-voltage and low power but not implementing the good performances.The thesis had done the widespread investigation and study to the domestic and foreign's technologies of analogy low voltage and low power,and analyzed the principles of work,merts and shortcomings of these technologies,based on the absorption of these technologies,it designeda 3.3V low power rail-to-rail CMOS operational amplifier.When designing input stage,in order to low the power consumption and stable the output voltage of common mode,it used the traditional differential input pair and designs the common-mode voltage feedback circuit.In the bias circuit design,the current mirror load did not use the traditional standard cascade structure,but used the low voltage,wide-swing casecode structure which was suitable to work in low voltage.When designing output stage,in order to enhance the efficiency,it used the push-pull common source stage amplifier as the output stage, the output voltage swing basically reached rail-to-rail.The thesis used the Miller compensate technology with a adjusting zero resistance to compensate the operational amplifier.The circuit design is realized in CSMC 0.6μm CMOS technology and HSPICE simulation results of CMOS indicate that it consumes only 9.6 mW and the delay time is only 16.8 ns,achieves the dc open gain of 83.78 dB,unity-gain frequency of 52.8 MHz,and the phase margin of 76°for a 5-pF-load capacitance and a 20 kΩload resistance,while the simulation of BiCMOS design consumes 10.2 mW and the delay time is only 16.8 ns,achieves the dc open gain of 83.78 dB,the unity-gain frequency of 75 MHz and the phase margin of 63°with the same load.All of pre-defined specifications are satisfied with the simulation results.