The Multi-DSP Array System For Signal Analysis Design

With the development of technology in communication and digital signal analysis, DSP has widely used than before. Signal analysis is a means of reasoning through the reverse analysis of signal technology. For signal analysis, DSP chips have a wide range of applications. Now for the more complex the signal change and faster signal transmission, multi-DSP parallel system is more important than single DSP system.Computer power and data transmission rate are the most important object in equipment for signal analysis. Base on the "DSP-based array for signal analysis and processing equipment" project, this paper propose a multi-layered structure of DSP array architecture and PCI Express architecture for signal analysis and processing equipment, with sum up the DSP chip development and the multi-DSP parallel system structure.In DSP selection, we compare many providers'DSP and some DSP chip's internal structure. At last, we use the ADSP TS-201 DSP chip, provide by AD Inc. This chip's computer power can up to 3.6GFLOPS, and has many interfaces used to connect with other DSP chips. Use this DSP can easily construct multi-DSP parallel system.In multi-DSP parallel system, summarize the shared bus connection type and point-to-point connection type, base on the system's expansibility and flexibility; we use a multi-layered construction of the DSP array. We use shared bus connect 4 DSP, which we called a multi-DSP cluster. Using the shared bus, can make the most of each DSP chip's computer power. Between the multi-DSP cluster, we use linkport interface. Using this interface, the data transmission date can up to 500MB/s, and can compose a larger loosely coupled multi-DSP array.In the whole system, we use the PCI Express architecture. Each module use a 4 lane PCI Express endpoint connect with upper computer, which is implementing with ALTERA FPGA. Using this interface, the data transmission date can up to 1GB/s in theory. Also we use the ASIC chip to construct a PCI Express switch architecture, for system's expansibility.At last, we design a test platform by using some system modules. We run a FFT parallel arithmetic and accord advantage stat parallel arithmetic on the test platform for testing the hardware platform's performs. We bear out that the hardware platform is mostly filling with require of signal analysis.