Study On The Digital IF Receiver And Control System For Radar Altimeter

Receiving and controlling unit are the important components for radar altimeter. In this dissertation, A Digital IF receiver is implemented by FPGA and DSP, which is characterized by the minimum DC error, the high consistency in amplitude, and the high orthogonal degree for IQ. It can decrease the complexity of radar system while increase its precision. FPGA devices are rich in their IO pins, which can be configured to almost all the standards of interfaces. I/O pins are suitable for controlling in altimeter control system concurrently. FPGA, which is abundant in its registers and logics, can operate at high frequency. So FPGA is appropriate to implement the precise timing control in the system. Therefore, it is important to apply FPGA technology into the altimeter control and receiver system.The dissertation involves the following aspects:(1) The mechanism of controlling system and receiving system for radar altimeter is studied. The radar altimeter control system is analyzed in detail. The control timing unit of radar altimeter is realized in a xc2v3000 FPGA., The test results prove that it is accorded with the requirement.(2) Based on the study of the digital IF receiver, radar altimeter receivers in both wide band and narrow band are discussed, and then the realizations are optimized. The simulation results in MATLAB which proved the correctness of the design are given out.(3) The two receivers are then implemented in a virtex xc2v3000 FPGA. The results simulated in MATLAB and MODESIM show that the IQ phase orthogonal error of wide band receiver is lower than 3°and the amplitude error is lower than 0.3dB. In comparison, the IQ phase orthogonal error of narrow band receiver is lower than 0.7°, and the amplitude error is lower than 0.02dB.