Research And Hardware Implementation Of The Sub-pixel Image Contour Extraction Algorithm

With the development of computer technology, computer vision applications are widely used. As the important part of the computer vision processing, image contour extraction attracts more and more attention especially for the real-time image processing and super image processing. This paper focuses on a high speed sub-pixel contour extraction algorithm and accomplishes its hardware implementation based on FPGA. The design is applied to the detection of PCB production and improves the quality detection efficiency.The main contents are as follows:Research on sub-pixel and image contour detection. This part focuses on the basic concept of sub-pixel and contour detection.Analysising and choosing the contour extraction algorithm. We made comparison on susan factor contour detection algorithm, canny factor contour detection algorithm and ContourExtractor2DimageFiler algorithm. Through analysis of the advantages and disadvantages of these algorithms, the ContourExtractor2DimageFiler algorithm is chosen to implement our project.Hardware card design. The hardware platform needed by the algorithm implementation is designed based on the Spartan-3FPGA from Xilinx company.Hardware implementation of the algorithm. According to the algorithm, the MicroBlaze processor together with the synergistic processing modules is adopted to implement the algorithm on the hardware platform. The driver of the hardware board and simple DMA driver is programmed to accomplish the software part of the algorithm.