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Design And FPGA Implement Of MT-DS-CDMA If Transceiver

Posted on:2010-02-05Degree:MasterType:Thesis
Country:ChinaCandidate:C H JinFull Text:PDF
GTID:2178360278465720Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
With the development of OFDM and CDMA technology, multi-carrier CDMA which is a combination of them in mobile communication systems becomes a trend. In the IF transceiver based on the MT-DS-CDMA system, digital filter and digital modulation/demodulation are both important components. They are not only the important branch of signal and information processing, but also the basic function of digitization. Due to the characteristics of FPGA, using FPGA chip to implement the digital signal processing has become the best way.This paper firstly introduces basic principles and performance indicators of digital filter, and focuses on principles and design methods of FIR filter, as well as RRC shaping filter based on FIR filter. It also introduces MATLAB design methods and implement method. Then this paper summarizes basic principles and performance of digital modulation/demodulation, and introduces M-PSK modulation, and focuses on the performance of modulation mode which based on BPSK and QPSK in DS-CDMA system, and demonstrates that spread/despreading spectrum does not affect modulation/demodulation.According to the principle of FIR shaping filter and modulation/demodulation, this paper proposes a design plan of the FIR shaping filter and complex modulation/demodulation in the IF transceiver based on MT-DS-CDMA system and the performance requirements.With the study of FPGA implement process, this paper introduces IP core in FPGA, and then completes the complement of the FIR shaping filter and complex modulation/demodulation based on the chip of XILINX's Virtex-4 family in the Xilinx ISE development environment. With ModelSim simulation and comparison of functional simulation, timing simulation and C language simulation data, the correctness of the implement is verified. Finally system hardware test using ChipScope software, Logic Analyzers and Bit Error Tester is completed to verify the correctness of FPGA implement. The results meet the requirements which the FIR shaping filter has a flat-band and a 40dB band rejection, and the frequency of four sub-carriers of about 20MHz bandwidth base-band signal is correct.
Keywords/Search Tags:MT-DS-CDMA, FIR filter, complex modulation/demodulation, FPGA
PDF Full Text Request
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