128 Qam Modulation Demodulation System Key Technology Research And The Fpga Implementation

With the development of communication technologies, many wireless communication standards have been applied. With the growing tension in the frequency spectrum resources, Quadrature amplitude modulation (QAM) has been widely used for its high spectrum utilization. Since the nineties of the last century, Theory of all-digital receiver has been developed with digital signal processing technology used in the analog processing area. All-digital receiver uses a local sampling clock, timing recovery, carrier recovery and the symbol decision can be completed within digital signal processing unit. The development of all-digital receiver technology has accelerated digitization and integration of the communication system.Traditional digital microwave communication systems have the shortcomings of insufficient channel capacity. The background of the research in this thesis is the base station microwave communications. In28MHz bandwidth, digital128QAM modulation and demodulation system with transmission bit rate of155Mbit/s were designed and implemented. My work is as follows.First, according to the parameters required system solutions were elaborated. Timing recovery is closed-loop structure based on Gardner algorithm.channel equalization is adaptive using constant modulus (CMA) algorithm. In order to recover the carrier frequency, the polarity decision loop is used in capuring mode and DD loop in tracking mode. Simulation result in MATLAB show that the system meets performance requirements.Third, Relying on the Software Defined Radio platform, An FPGA-based hardware implementations was proposed, algorithms in modulation is inplemented in use of DA converter chip DAC5687of Ti and the FPGA chip EP3C120F780I7of Altera cyclone Ⅲ Series, while all-digital demodulation algorithms by the AD converter chip of ADS62P24of TI and EP3C120F780I7. In this dissertation, FPGA subsystem is acturally a multi-clock system, and multiple clocks are distributed to different modules according to its requirement.At last, According to the function definition and timing constraints, FPGA design of some key modules is completed, optimization are made on both the speed and resource. The timing analysis reprot and simulation results in Modelsim show that FPGA design of modules can meet the timing requirements, with correct logic functions. On-board debugging were also completed, and the results show that desired signal processing functions were achieved by the FPGA chip.