High Performance Erroe Amplifier Design Based On BUCK DC-DC Converter

Due to their merits of wide input range, high efficiency, small in size and light in weight ect., switching power supplies are gaining more and more application areas in today's modern world, ranging from domestic equipments to sophisticated communication and data handling systems, especially in portable devices, they have unsurppassable advantages. In return, the rapid development of products in corrresponding application areas requires the power supplies to have better performances. The robustness of switch-mode power supplies directly affects the performance of electronical devices. As one of the most important parts of swtched mode DC to DC converters, error amplifier has significante influences on the voltage control loop's stability. Thus this paper focuses on the design of high performance error amplifier for DC-DC converters based on system requirements analysis.A buck DC to DC converter was concerned, an error amplifier for the buck converter was designed from the points of view of system stability, load regulation and response speed requirements. At the first place, the Buck DC-DC converter's voltage control loop stability and pole-zero analysis was done based on a small signal model of the voltage control loop, the compensation scheme was proposed and the key specifications of the error amplifier were determined to satisfy the control loop's requirements. The validity of the error amplifier's specification desgin was verified with Hspice simulator on system level. According to the system level design of the error amplifier, a transistor level implementation was proposed, the main circuit of the error amplifier was implemented by a two stage BJT operational transconductance amplifier (OTA). Two matched resistors were added to the active load of the differiential amplifying stage, making the open loop small signal DC gain and the transconductance of the differiential amplifying stage adjustable, thus it is easier to obtain the system required open loop small signal DC gain and the transconductance of the error amplifier. In addtion, a dynamic transconductance adjuster was added to the OTA to enhance the large signal transient response of the system's control loop. At last, the error amplifier is ameliorated according to the system level requirements analysis, system soft-start and maximum output inductor charge current control circuits were added to its main circuits.The transistor level implementation of the error amplifier was based on UMC BCD process. Simulations were performed in using Hspice simulator to verify the error amplifier proposed. Process model influences were considered in the simulation, making the simulation results much closer to reality. Simulation results indicate that the error amplifier designed satisfies the system stability, load regulation and transient response speed requirements and well realizes the system soft-start and maximum output inductor charge current limit functions. Moreover, it has high PSRR and CMRR.