Design Of DC-DC Controller Chip For High Power Density Power Module

With the popularity of smart wearable devices and various portable electronic devices,smaller size and longer battery life are now one of the goals commonly pursued by the industry.As one of the indispensable DC-DC converters in electronic equipment for power conversion,Buck converters require greater power density to meet people's needs.Therefore,it is the power management chip designer to increase the power density of Buck converter chips.Major challenge.In order to increase the power density of Buck converters,keeping the switching frequency of the Buck converter high enough can greatly reduce the area of the power switch tube on the basis of high voltage and high current.Therefore,high switching frequency is the basis for improving the power density of Buck converters.Buck converters that use the traditional valley current mode COT control mode generally use type II compensation.In order to meet the sampling theorem,the loop bandwidth is set based on the lowest switching frequency,which causes the transient response speed to change at high frequencies.In order to solve this problem,this paper proposes that the valley current mode COT structure using the switched current error amplifier does not require an additional compensation network,which saves chip area while achieving adaptive bandwidth,and improves the transient response speed of the Buck converter at high frequencies.In addition,the switching frequency of the Buck converter in the traditional valley current mode COT control mode will shift under heavy load.In this regard,this article uses frequency stabilization technology to ensure that the Buck converter achieves frequency stability under high currents.This paper first designs a valley current-mode COT Buck converter based on PLL modulation.It adopts dual output structure to improve the power density of the chip.It supports 180° out-of-phase operation.The on-chip integrated power switch tube can be adjusted by adjusting the switching frequency.It can be changed by an external resistor,or an external clock can be used for synchronization.Input voltage 3.6?20V,output voltage 0.6?6V,switching frequency support 0.5?4MHz,single channel maximum load current is 3A,support input voltage over-voltage protection,output voltage over-voltage and under-voltage protection,over-temperature protection and Burst working mode,etc.Features.This article introduces the core sub-modules of the chip,and gives the simulation waveform of each sub-module,which basically meets the design requirements.It also models the entire switching frequency synchronization module in loop theory and gives a compensation method.Then a brief introduction was made to the overall chip architecture,showing the overall simulation waveforms of chip startup,work efficiency,load step and protection functions,to ensure that the chip can maintain normal operation under various conditions.Finally,the layout of the chip is introduced.In order to further improve the power density of the chip,this paper also proposes a high power density Buck converter design using a switched current error amplifier.This error amplifier does not require off-chip compensation in the Buck structure.It can keep the system stable,save the chip area,and have a higher power density;at the same time,the bandwidth of the error amplifier changes adaptively with the change of the switching frequency,and still has better stability and transient response speed at high frequencies.Compared with RBCOT and the traditional valley current mode COT control mode,the valley current mode COT structure of the switch current error amplifier realizes on-chip frequency compensation,saves off-chip components,and can realize multi-channel parallel current sharing,and has Faster transient response speed.This paper uses 0.18?m BCD technology for circuit design.The simulation results show that,at 6MHz and 1MHz switching frequencies,the corresponding selection of 10?F and 70?F output capacitors can achieve loop stability and achieve adaptive bandwidth.Under the 6MHz switching frequency,the upper and lower step transient response times are 6.3 ?s and 5.5 ?s respectively;at 1 MHz switching frequency,the upper and lower step transient response times are 27.7 ?s and 28.4 ?s respectively.