The EDA Verification For"Buffer Management" Logic

"Buffer Management"Logic is a kind of digital logic circuit which is used to request and release address of SRAM (Static Random Access Memory). According to the application in swich fabric chip, this paper mainly tests the functions such as register test, reset test, request address, release address, the output way choosing function, the buffer sharing in different working modes, and line rating function.VMM(verification methodology manual for SystemVerilog) supplies some"basic objects"which are often used. It has an effective verification environment templet, so that it will reduce verification time obviously. It defines some standards which can make creating reuse testbench and modules be possible. SystemVerilog is an intuitionis, Object Oriented, advanced language which can generate random data more effectively. Above all it will make designing the testbench easy, effective, proper and practical.This paper discusses how to use VMM and SystemVerilog to design an automatic verification environment that is used to test the"Buffer Management"logic. In the end an EDA(Electronic Design Automation) verification is realized, which is mainly to do random test, the direct test is only assistant way, and make sure the code coverage is 95%, the condition coverage is above 90%. During the verification, many difficult problems are solved, such as the produce of random data, the testing of interface timing, the package and automatic comparison of cycle data, the environmental self-test technology of non-design code, the writing and debugging of general test case template, and so on. At last a simple and efficient verification platform is established.