Research And Design Of LDPC Codes Encoder For Terrestrial Digital Multimedia TV/Handle Broadcasting

LDPC code is the most superb sort of error control codes,especially when it has long code length and adopts soft decoding method. This code can get very low BER in extremely noisy circumstances, so it is the perfect candidate for wireless and space telecommunications. In DMB-T FEC has applied BCH+LDPC cascade form and LDPC code palys an important role in the FEC module. Much work has been focused on the constructing and encoding methods and constructing algorithm becomes one of the research hotspots.The main work are as follows:(1) In this paper we have done a research on algorithms of constructing LDPC codes ,sum-product and minimum-sum iterative decoding for immediate simulations;(2) Find out the perfect cyclic difference sets with q < 50 utilizing the number sequence for constructing and simulating LDPC codes. Bring forward an algorithm for LDPC construction based on Vandermonde matrix and under the AWGN channel BER with 10^-7@0.5 code rate has been achieved;(3) In terms of hardware implementation ASIP architecture is introduced based on DMB-T standard. We make some modifications on the micro architecture and micro instructions to make it compatible to realize the function of the channel encoder by combining the performance of ASIC with the variability of GPP. We has finished the concerned RTL design and logic simulations. The optimized encoder supports multiple code rates;(4) In Syplicity ,We use FPGA xc4vsx35 as synthesis device and the throughput could reach 144.64Mbps while 72.89MHz clock has been applied. High throughput makes it possible to realize the multiplex transmition. Now we are verifying our design in FPGA board xc4vsx35.