FPGA Firmware Development For ALICE EMCal Electronics System

With the rapidly development of the ASIC technology,the Field Programmable Gate Array(FPGA) device has been widely used in the high-energy physics detectors.At present,the Large Hadron Collider(LHC) is a physical science experimental device with highest energy in the world.A Large Ion Collider Experiment(ALICE) is one of four physical experiments on LHC.Electro Magnetic Calorimeter(EMCal) is a sub-detector on the ALICE experiment.The development of the FPGA firmware for Front End Electronics(FEE) card and Trigger Region Unit(TRU) of EMCal electronics system is the main work of this thesis.EMCal is a kind of sampling calorimeter with 12672 WLS readout Pb/Scintillator (Shashlik type) towers.The light from WLS is converted into current by the Avalanche Photo Diode(APD) and pre-amplified by the Current Sensitive Pre-amplifier(CSP). Each FEE card implements shapers and ALTRO chips which integrats ADCs,digital processing logic and storages to process step signals outputted by 32 CSPs concurrently. FEE card also includes fast shapers with a shaping time of 100 ns to provide fast-or signals for TRU.Twelve 12-bit,8-channel serial Analog-to-Digital Converter(SADC) on the TRU sample 96-channel fast-or signals from 12 FEE cards and output 480 Mbit/s serial data flow.The FPGA on the TRU is dedicated to de-serialize the serial data flow, implement the peak-finder algorithm and generate a 40 MHz level-0 trigger signal. The main work of the thesis is divided into four parts which will be described hereafter respectively.◇Development of Generic core-level system for FEE and TRUThe EMCal development is a long-term process,the system upgrades will be carried out continuously during the development process.Hence,the scalability is very important for FPGA firmware design.In order to add new functions and optimize the previous functions for FEE,it is necessary to re-design the system architecture for FEE FPGA.In addition,FEE and TRU communicate with high-level system through same protocols and use same board monitoring strategy.So,the design of a generic core-level system is necessary and feasible.This generic core-level system achieves common functions for FEE and TRU.The system is highly scalable and easy to insert new modules.◇Development of Sparse Readout module for FEEStudy shows that addressing empty channels occupant a lot of time during the readout of an active event on EMCal.The Sparse Readout module is dedicated to scan all the channels before event readout operation and inform the DAQ to read the channels with data.◇Development of Serial Analog-to-Digital Converter(SADC) debugging module for TRUDebugging the firmware always occupant a lot of time during the developing process. The SADC debugging module is dedicated to minimize the debugging time of modules related to the SADCs on TRU as far as possible.This debugging module has integrated all the debugging functions for SADCs.One can switch the debugging modes by setting two registers remotely.◇Development of Tunable Phase Shift module for TRUThe Downhill finder algorithm which will be implemented in the FPGA on TRU requires the synchronization of the ADC sampling clock and the peak of the fast-or signals.The Tunable Phase Shift module is designed to fix that synchronization problem.For 40 MHz sampling clock on TRU,it can adjust the phase with defined steps.The single-step phase-shift is 1/256 degree;the total range of phase-shift steps is from -51 steps to+51 steps.More in general,scalability,reusability and self-debugging function are the key features of FPGA firmware developing covered in the present thesis work,where scalability refers that one can insert new functional modules under the architecture of the generic core-level system;reusability refers that all the modules had been designed in "IP core" style;self-debugging function refers that a lot of debugging function for firmware debugging and hardware testing had been added into the design.