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Design Of Dual-Band LNA For GPS And Beidou Dual-Mode Receiver

Posted on:2010-11-07Degree:MasterType:Thesis
Country:ChinaCandidate:J SuFull Text:PDF
GTID:2178360275973286Subject:Microelectronics and Solid State Electronics
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Currently, several wireless standards are using and new standards are coming up to markets continuously. To meet the market demand, a single radio mobile RF device that can handle the multi-mode/multi-band signals is realized. The realization of multi-band LNA in multi-band wireless receiver has become an important hotspot.RF receiver consists of analog and digital parts. These two blocks were fabricated by different processes before. CMOS process is gradually matured after long time efforts made by researchers, this kind of process can now be used in RF chip part and make a single chip with analog and digital integration for RF receiver, this technology reduce the cost and increase the integration of the system.Since the Beidou and GPS (Global Positioning System) are widely used in our country, a dual-band LNA working at 1.57GHz and 2.49GHz was designed based on SMIC 0.18μm RF CMOS process in this paper. Firstly, the high frequency characteristics of the capacitor and inductor were introduced, and their high frequency models were provided, the noise characteristic of the MOSFET has been analyzed, and its high frequency equivalent circuit was present. Secondly, a concurrent dual-band LNA which can work at dual-frequencies is designed. After analyzing and comparing several common structures of CMOS amplifier, the structure of cascode with source inductive degeneration is chosen as the major part for dual-band LNA. Especially according to the requirement that the designed LNA should work at the dual-band simultaneously, this paper focuses on the design of the input/output impedance matching network. Thirdly, the designed concurrent dual-band LNA was simulated with the simulator SpectreRF in Cadence. The results show that the dual-band LNA has a voltage-supply of 1.8V, NF in the two bands is less than 4.1dB, voltage gain is more than 16 dB, s11 and s22 are less than -18 dB, IIP3 is more than 0dBm, all the performance meet the requirement. Finally, the layout of the concurrent dual-band LNA is completed by using the layout tool of Cadence Layout Editor and the post-simulation was done.
Keywords/Search Tags:CMOS, RF Receiver, LNA, Concurrent, Dual-band, Linearity
PDF Full Text Request
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