The Research Of GPS C/A Code Acquisition By FFT Algoriyhm Based On FPGA Chip

As China's second-generation navigation system is being built,the application of satellite navigation will be spread to all industries,and the satellite navigation receiver with independent intellectual property rights has been the research hotspot in the field. In receiver design,for mature technology the ASIC chip,which is a dedicated chip and can not be changed once manufactured,will be used for mass production.However,in the studying of receiver,especially in the studies that need to use the receiver platform to improve receiver performance,the use of FPGA(Field Programmable Gate Array) chips is extremely convenient.Once the results of research on FPGA are mellow,they can be easily transferred to the ASIC chip for mass production.This issue is to achieve the hardware circuit of the GPS parallel acquisition based on FPGA,and focus on the design and implementation of one GPS capturing channel.GPS signal acquisition time is a key factor in GPS receiver performance,especially in the high dynamic,real-time applications or in capturing weak GPS signal areas. Therefore,the parallel FFT-based fast capture method has been proposed that is based on the sliding correlation method.The system has been used of top-down method to design system functions and the overall structure,and used of bottom-up approach to achieve and verify the system and functions.The system has been developed on the Xilinx's Spartan 3E starter board by using Verilog HDL program in the ISE 9.2i development environment.And the GPS IF signal generator platform has been designed by using Nemerix's GPS RF chip NJ1006A.The platform can be real-timely output GPS digital IF signal whose sampling frequency is 16.367MHz.The theme is based mainly on sampling rate conversion and FFT to resolve the coarse acquisition of C/A code in GPS signal.The key of the method is to convert signal rate from 16.367M to 1.024 M by using averaging technique,then get coarse pseudo-code phase(accuracy of about 1/4 chip) and Doppler carrier frequency from coarse acquisition of C/A code by utilizing mature 1024 points FFT IP core,which is in line with the requirements of GPS tracking.At the same time,because FFT algorithm is the resource for time to increase the speed of GPS acquisition.Therefore,in design,the theme has been reasonably used of FPGA design concepts and techniques to optimize system.Based on practical requirement,the paper has given principles,structure and simulation results of every system module in detail.Finally,the system can reduce hardware resources,and quickly, efficiently realize the GPS C/A Code acquisition.The result is a part of receiver signal acquisition algorithm in the subject of National 863 "Research on The New Technology to Increase GNSS Receivers Performance Using Multi-path Signals"undertaken by GNSS Institute in Dalian Maritime University,and has a certain reference value for the design of the receiver.