Study On The Algorithms Of DCT-Ⅱ Coefficients Based Image Sampling Rate Conversion And Its Architecture Design

Study on the Algorithms of DCT-II Coefficients Based Image Sampling Rate Conversion and Its Architecture Design Abstract With the development of computer, multimedia, signal compression and HDTV(High Definition Television) technology, the display formats of image have become diversified and also comply with corresponding standards respectively. Each standard has defined a set of display formats of its own, however they may not be mutually shared. On the basis of these standards, a variety of video products have come into being. On the other hand, along with the progress in multimedia technology and the enlargement of its application, it is desired that equipment with different display formats can readily exhibit various types of image or video signals. As a result, a deep investigation should be made for the sampling rate conversion of images. Meanwhile, many video compression standards such as MPEG-1 and MPEG-2 employ DCT(Discrete Cosine Transform) and IDCT(Inverse Discrete Cosine Transform) in coding and decoding. Besides, since MPEG-1 and MPEG-2 have already been extensively utilized as the standards of video streams and MPEG bitstreams transfer DCT coefficients instead of original video signals, so if the sampling rate conversion can be conducted directly by using the DCT coefficients, it will save the processing time and lower the computational complexity which has extensive practical significance. Based on the EIDCT algorithm proposed by Yuh-Feng Hsu and Yung-Chang Chen, it has been proved in this paper by the signal processing theory that EIDCT can be applied both for interpolation and decimation, thus becoming a unified algorithm for interpolation and decimation and for integer and fractional sampling rate conversion. At the same time, the VLSI(Very Large Scale Integration) implementation method suggested in the original paper has been improved for applicable hardware implementation. The work done in this paper is as follows:1) A research has been made on the DCT coefficients based algorithms in the literature with comparison between them and EIDCT is chosen for hardware implementation(cf.: Chap. 2 and 3). 2) EIDCT is only employed in the process of interpolation(upsampling) in the original paper but is extended to decimation(downsampling) in this paper(cf. : Chap. 3). 3) A recursive algorithm has been proposed in the original paper for VLSI implementation of EIDCT. Its artifacts are designated and the architectures for EIDCT are suggested in this paper. Since the problem of power dissipation has become an important point worth great notice on accout of the advances in the process of IC(Integrated Circuit), the computational complexity is extremely emphasized when considering the hardware implementation, because it directly influences the power dissipation of the circuits(cf. : Chap. 4). The main contributions of this paper are: 1) The EIDCT algorithm is extended to the process of decimation by taking into consideration the aliasing effect in the frequency domain, thus the image sampling rate conversion can be applied by the same formula(cf. : Chap. 3). 2) A recursive algorithm has been proposed in the original paper for VLSI(Very Large Scale Integration) implementation of EIDCT, but it takes a large number of operations and the hardware cost is rather high, so two new hardware implementation algorithms of EIDCT and the corresponding architectures are propounded from the aspect of lowering the computational complexity, which drastically reduces the numbers of multiplication and addition needed, constructing a basis for the future chip design(cf. : Chap. 4). 3) Some papers give a fast algorithm of DCT-I and DST-I. Nevertheless, under certain circumstances, its computational complexity is rather high. Consequently, a new algorithm is proposed which greatly decreases the nontrivial multiplications needed in such circumstances(cf. : 4.1.3 and 4.1.4).