Study And FPGA Implementation Of MIMO Detection With Variable Parameter

Recent years, mobile communication has been developing rapidly all over the world. With the commercial deployment of 2nd generation, 2.5 genertion, 3rd generation mobile communication systems, it still cannot meet the increasing needs of the mobile users. Some countries have paied much investigation and development for the next-generation wireless communication system.WiMax 802.16e makes a compelling solution for providing the last mile connection in wireless metropolitan area networks. Its physical layer is based on the MIMO-OFDM technology. So the MIMO detection in the receiving side becomes one of the key point in the WiMax uplink. In allusion to this problem, MIMO detection algorithm is deeply studied, FPGA implementation of QRM-MLD-ASESS algorithm with variable parameter is realized, and a series strict performace tests of the implementation are given in this thesis.Firstly, MIMO detection algorithms, such as ZF algorithm, MMSE algorithm, are introduced in this thesis. BER simulation of the algorithm used in the Rayleigh channel is given, characteristic of the algorithm is summed up and compared to each other. Through plenty analysis of the algorithm performance, implementation complexity and the system target, a compromise solution is given which is making the QRM-MLD-ASESS algorithm into FPGA implementation.Then, a configuration solution to the FPGA implementation of QRM-MLD-ASESS detection algorithm with the good functionality, maintenance, test performance, extend performance and variable parameter is proposed in this thesis. The result shows that a good throughput of the proposed configuration can be achieved. In the FPGA implementation, the RTL code is implemented by Verilog HDL. The functional simulation is given by ModelSim6.0 EDA software, the analysis synthesis, fitter, assembler, and timing analyzer in Quartus II7.1 are also used to test the implementation resolution.Hardware implementation is presented and the result is identical to that from ModelSim test on functionality. Experiments show that the FPGA implementation configuration proposed in this thesis work the way it should be.