Research And Implementation Of Low Bit Rate Speech Vocoder Based On FPGA

Digital speech communication is the fastest growing and the most widely popular business in the current information industry. As one direction of the digital speech signal processing, compression and coding of the speech signal are most closely associated with the communications areas. In the existing speech coding, the Mixed Excited Linear Prediction (MELP) algorithm in the 2.4 kb/s bit rate of the United States federal standards has achieved better voice quality and has broad application prospects.As a fast and efficient hardware platform, FPGA has the unique advantage in digital signal processing and communications. Modern large-capacity, high-speed FPGA has been embedded in DSP module such as high speed and reconfigurable RAM, PLL, LVDS, LVTTL, and hardware multiplication accumulator, etc. Using FPGA to achieve digital signal processing can solve parallel and speed, and the DSP system based on FPGA becomes very easy to modify, test and upgrade hardware for its flexibly reconfiguration.The research and design of the Mixed Excited Linear Prediction vocode FPGA based is expatiated in this article. Firstly, it introduces the development of speech coding, along with the significance of the low bit rate speech coding. Then the idea of modeling and realization process by using DSP Builder in Matlab is proposed. Finally, it emphasizes the design process of MELP vocoder. We can work out the key module such as filter, divide frame and adding window, and linear prediction analysis by using DSP Builder and Quartus II software.Then we can take DSP Builder to complete the function simulation of the encoding and decoding system under the circumstance of Simulink. We substitute the undesinged part of the vocoder system with the math model in Simulink, to simulate easily. The simulation result shows that the synthetical signals fit well with the original ones, and the quality of the speech got from the vocoder is good.