The Hardware Design And Realizatian Of Distributed Flight Test Bus System

Along with the astronautics technology's unceasing development, the complication and the modernization of aero-product are advancing, and they depend on the advanced test methods more and more. Along with the technology of computer network and distributed test system developing, they provide good conditions for the research of Real-time distributed test system of plane. Flight test system is always different from other test system, which is very rigorous to requirement of system bus, e.g. real-time performance, higher bandwidth. So most flight test systems both in the world are consistent to design and implement a special bus to achieve the goal, but technology of these test bus isn't open, and doesn't use a common transmission medium. So it's impossible for the users to extend its functions and integrate its systems.Nowsdays Ethernet is popular and practical for data communication in Internet, although it has a problem of data conflict, but it might solve through the time sharing transmission mechanism. Ethernet which solves data conflict is completely capable of flight testing. And its mature techniques, rapid speed, low cost and good compatibility, the Ethernet must make a good base to develop a feasible flight test system.Distributed flight test bus system in this topic designs base on the Ethernet.Synthesizing the actual request of flight testing, this topic proposes one kind of distributed flight test bus system's construction plan based on Ethernet technology, distributed technology, clock synchronization technology, bus technology and FPGA technology. It completes the general hardware platform design and the function realization. This paper focuses on solving the problems of general FPGA hardware platform's structure, inside and outside bus's definition and design, data gathering, PCM output and clock synchronization's design. The paper mainly includes the following several aspects:①Referring to the advanced KAM-500 flight test system, propose one kind of distributed flight test bus system's structure, analyze the composition of its hardware system, complete the hardware circuit design of system control board, functional simulation board and back board, and realize a small-scale hardware platform of flight test bus system, in deeply researching existing distributed flight test system.②In researching the existing test bus structure, design the outside bus by using the Ethernet to realize the gathering units'synchronization control and the data transmission. It uses the time sharing transmission mechanism to avoid the data transmission conflict. Design the inside bus by using Fieldbus thought to realize the data transmission in the gathering unit. The realization of inside bus uses the hardware module, which enables system's data transmission to achieve a higher real-time and a smaller vibration. Such bus structure enhanced system's extendibility greatly.③The system control board realizes the local data with other gathering unit data exchange and the data time sharing control under the SOPC system. And realize the inside bus's transmission and control by the custom instruction. The AD board and the PCM board realize data gathering and the output by the hardware functional modules.④The clock synchronization is also one of flight test system's key technologies. Flight test system in the past used the IEEE1588 standard to realize the clock synchronization.Although it can achieve very good synchronization, but its realization is quite complex, especially in no operating system's situation. The clock synchronization of this system reduces and improves the IEEE1588 standard by using its idea, and realizes in SOPC system. It makes clock synchronization to realize simply.Finally it carries on the test to the distributed flight test bus system researching in this paper. The test result indicated: the flight test system's structure is nimble and reasonable; the system hardware is reasonable and good versatility; the correspondence of outside bus by time sharing control and correspondence of inside bus by FPGA cause the data transmission to be stabler. The clock synchronization algorithm has high precision, to satisfy system's request. This system already has been tried at the flight experimental for the airplane, and has made the very good progress.