Font Size: a A A

FPGA Design And Implementation Of Viterbi Decoder In High-density Optical Disc

Posted on:2008-05-22Degree:MasterType:Thesis
Country:ChinaCandidate:F S ZhongFull Text:PDF
GTID:2178360272968116Subject:Computer system architecture
Abstract/Summary:PDF Full Text Request
In the high-density optical disc system, the normalized information density (S) exceeds 5.0, which is 4.6 in the DVD. Because of the high density, there is more intersymbol interference (ISI) in the readout signal. The detection of the readout signal must be improved because the threshold detection used in DVD is not available for the high-density disc any more. The partial response maximum likelihood (PRML) detection increases the using of the bandwidth and decreases the requirement of timing precision by making use of the ISI rationally. PRML has been widely used in the magnetic channel. The Viterbi algorithm is one of the best algorithms for implementing the maximum likelihood (ML) detection.The characteristics of disc channel are very significant for the selection of partial response (PR) polynomial. The PR polynomial that is 1 + 2 D + 2 D~2 + 2D~3 + D~4 is selected according to the mathematical model and the characteristics of the next-generation versatile disc (NVD) channel. A trellis diagram with 8 states is established according to the PR polynomial and the characteristic that the minimum of the running length (d ) is 2 in the disc modulation code. The Viterbi algorithm is introduced by an example, including the calculation of branch metrics, the management of survived path and the decision and output of the decoding.Based on the FPGA, Viterbi decoder is implemented in Verilog HDL. The modules of Viterbi decoder are simulated by Quartusâ…ˇ5.0, including the Branch Metric Calculator Unit, the Add-Compare-Select Unit, the Survived Path Manage Unit and the Decision-Output Unit. The test of the decoder consists of simulation in software and in-system programming (ISP) . Enormous data is used to test the Viterbi decoder.With the result of testing, the clock rate with which the decoder can process data perfectly can be up to 30MHz. The decoder can be used in the next-generation versatile disc channel.
Keywords/Search Tags:Next-generation Versatile Disc, Partial Response Maximum Likelihood, Viterbi Algorithm, Hardware Description Language
PDF Full Text Request
Related items