Driving Circuit Design Of Chalcogenide Random Access Memory

With the advantage of high read and write speed, more erase and write times, nonvolatile store, high density, small power and low cost, CRAM (Chalcogenide Random Access Memory) was deemed to be a new memory to replace the mainstream memory in market such as Flash memory, and used in computer and mobile communication widely.The purpose of this study is to design a current pulse driving circuit to achieve the read, erase and write operation of CRAM. The circuit can control mutual transformation of the storage element GST from crystalline to amorphous, address storage array, and simulate the read, erase and write operation. First, this paper starts at the basic work principle of CRAM. According to the functional and performance requirements, it is presented to establish the system module of CRAM'driving circuit, including Pulse-Width Modulation, read, erase and write current source, phase discriminator, etc. Then it realized the work module through specific circuit design, analyzed the performance of the circuit module in the theory and simulation. Finally, the entire CRAM driving circuit is presented for the overall system simulation and analysis to come to the circuit performance. The simulation results by the software Multisim shows that the read erase and write pulse amplitude is respectively 1.0V, 1.45V and 2.45V. The pulse width is respectively 40ns, 50ns and 30ns. Erase and write current is 150uA and 75uA, and read current is 5uA in the high resistance state. The system uses the 0.18um CMOS process and power supply voltage of 3V. It can drive storage capacity of 4Mb, with 8 input and output ports, and the highest rate of information access for 80Mb/s. when we supply timing signals to the system port, it can complete read, erase, write and address operation, produce excellent IO signal at the output ports. Thus, it can prove the external drive circuit of CRAM is feasible.