Application-Directed Cache Coherence Design

Chip multiprocessors continue to provide programmers with a coherent view of shared memory in hardware across all cores. At large core counts, maintaining coherence in hardware across cached copies of data is a challenge due to bandwidth and metadata storage consumption. A cache block is the basic unit for data storage and communication, chosen at design time to match average locality across a range of applications. Conventional hardware implements the coherence protocol using a fixed granularity (of a cache block) for all coherence operations. Coherence metadata is recorded for every cache block, and coherence permissions are also granted in cache block units. Metadata is typically proportional both to the number of cores and the amount of data cached.;Empirical analysis shows that applications typically exhibit a small number of sharing patterns, resulting in redundant information in the metadata. Similarly, considerable bandwidth is wasted due to a mismatch between application access granularity and the fixed granularity data and coherence communication.;This dissertation leverages the inherent patterns of data access and sharing behavior in applications to design protocols that eliminate the bandwidth and metadata storage waste in conventional coherence protocols. The sharing pattern-aware directory designs, which we call SPACE and SPATL, recognize and represent only one copy of the subset of sharing patterns exhibited at any given instant in an application. The resulting protocols eliminate the linear proportionality of metadata storage to the number of cores. The adaptive coherence granularity designs, which we call Protozoa, match data movement to an application's spatial locality and access behavior, supporting fine granularity sharing without increasing metadata storage needs. The application-directed approach allows bandwidth needs to track inherent application access and sharing behavior.