Design And Implementation Of AES Coprocessoer IP Core

This paper is supported by the pre-research project " Research in technology of high performance Network Processor "。In order to achieve higher performance, the author designed the special encryption/decryption module to process the data.In this paper, the author chose the AES algorithm as the encryption/decryption algorithm which would be realized in the chip of Network Processor, firstly elaborated some mathematics knowledge for studying AES algorithm. Secondly, the AES algorithm was described in this paper, including its encryption,decryption and KeyExpansion. Then the hardware design was carried through. The whole architecture,the function of the module and the relationship between the modules were researched. The AES module has been divided into three parts: encryption,decryption and KeyExpansion. The SBox,ShiftRow,MixColumn and AddRoundKey were also designed. Through the optimization, the problem that some complicated mathematics operation takes negative affect on the speed of data process had been resolved. The structure of MixColumn also had been optimized so that the resources used by polynomial multiplication were reduced greatly.In the process of simulation and verification, the author researched on the IP core of the Openrisc1200, designed the data_combin module and the asynchronous FIFO module, set up a verification system to simulate and verifiy the result. Then the author used the vector space supplied by Rijndael, made the AES IP core a serial structure which can encrypt the input data and then decrypt the data output by encryption. This work has proved the correctness of the encryption/decryption and established the foundation for the further research in hardware design in encryption/decryption in the chip of Network Processor.