Design And Implementation Of FPGA-based ZUC Encryption Algorithm IP Core

With the rapid development of Internet technology and the high popularity of mobile communications,a large amount of information is transmitted between networks every day,which contains a large number of individual users' private information and sensitive information concerning the confidentiality of the state,government and enterprises.Therefore,information security has become an issue that cannot be underestimated in today's society.In the field of information security,China started a little later than the western developed countries,but after decades of development,it has made rapid progress.In 2011,the ZUC algorithm which is independently developed by China was adopted by the international organization 3GPP as the next-generation broadband wireless mobile communication system international standard.This marks a major breakthrough in the field of commercial cryptography in China,which greatly enhances China's right to speak in the development of international cryptographic algorithm standards,and has played a very positive role in the development of cryptography in China.Based on the research of ZUC algorithm,this paper completes the design and implementation of FPGA-based ZUC encryption algorithm IP core.In the implementation,the pipeline optimization for the initialization stage of the ZUC algorithm is completed,at the same time,the speed optimization of the working stage of the algorithm is also completed,it makes the design in this paper complete the optimization of the algorithm in two stages,and significantly improves the maximum working frequency of the module.The 185.19 MHz operating frequency of the ZUC module is implemented on the Artix-7 xc7a100tfgg484-2.At the same time,from the perspective of improving the unpredictability of the initial vector of ZUC algorithm,an IV generation algorithm based on Logistic chaotic mapping is proposed and the corresponding communication frame structure is designed and it improves the security of the encryption algorithm in the application.At the end of the work,the various functional modules realized are integrated and perfected,and finally the FPGA-based ZUC encryption algorithm IP core is realized.In general,in the design and implementation process of the IP core,the hierarchical design method is followed,and the main functions are split into independent functional modules to be implemented separately,this improves design efficiency.The final completed IP core meets the design requirements in the simulation,integrated logic analyzer test,and finally the actual communication test with the host computer.